Japanese Patent Laid-Open Publication No. H5-308274 (“Patent Document 1”) discloses a CMOS level shift circuit. The CMOS level shift circuit disclosed in Patent Document 1 obtains a signal output of a high voltage level by a circuit configuration of a MOS transistor having a small withstand voltage between a gate and a source. Also, Patent Document 1 (see paragraph 0008) discloses that, in general, a MOS transistor can easily increase a withstand voltage BVSD between a source and a drain but has difficulty in increasing a withstand voltage BVGS between a gate and a source, due to the structure of the MOS transistor.
FIG. 10 shows a CMOS level shift circuit illustrated in FIG. 1 of Patent Document 1. In FIG. 10, a gate G of an n type MOS transistor 14 is connected to an input port IN of an inverter 8, and a signal having a low voltage level is input to the input port IN of the inverter 8. Respective gates G of n type MOS transistors 11 and 16 are commonly connected to an output terminal of the inverter 8. Respective sources S of the n type MOS transistors 11, 14, and 16 are commonly connected to a ground terminal Vss. Also, a drain D of a p type MOS transistor 10 is connected to a drain D of the n type MOS transistor 11, and a drain D of a p type MOS transistor 13 is connected to a drain D of the n type MOS transistor 14. Respective gates G of the p type MOS transistors 10 and 13 are commonly connected to a prescribed bias voltage VB. The bias voltage VB is selected as VDD-BVGS. Here, VDD is a power supply voltage, and BVGS is a withstand voltage between the source and gate of the p type MOS transistors 10 and 13.
In FIG. 10, a source S of a p type MOS transistor 10 is connected to a drain D of a p type MOS transistor 9 and a gate G of a p type MOS transistor 12. A source S of the p type MOS transistor 13 is commonly connected to gates G of the p type MOS transistors 9 and 15 and a drain D of the p type MOS transistor 12. Respective sources S of the p type MOS transistors 9, 12, and 15 are commonly connected to the power supply voltage VDD.
According to Paragraph 0018 of Patent Document 1, the bias voltage (VB=VDD−BVGS) is applied to the gates G of the p type MOS transistors 10 and 13. Thus, the voltages between the sources and gates of these transistors are lower than the withstand voltage BVGS.
According to Paragraphs 0019 and 0020, respective sources S and drains D of the p type MOS transistors 10 and 13 are connected between respective drains D of the p type MOS transistors 9 and 12 whose sources S are connected to the power supply voltage VDD and respective drains D of the n type MOS transistors 11 and 14 whose sources S are grounded, and the prescribed bias voltage, which does not exceed a difference between the power supply voltage VDD and the withstand voltage BVGS between the source and gate of the p type MOS transistor, is applied to the gates of the p type MOS transistors 10 and 13, whereby the voltages between the sources and gates of the p type MOS transistors 10 and 13 are lower than the withstand voltage BVGS. Accordingly, the CMOS level shift circuit is configured with a MOS transistor having a small withstand voltage BVGS between the source and gate. In other words, Patent Document 1 proposes a circuit configuration in consideration of the withstand voltage between the sources and gates of the p type MOS transistors 10 and 13.
Japanese Patent Laid-Open Publication No. 2002-190731 (“Patent Document 2”) discloses a level shift circuit and a semiconductor device. The level shift circuit disclosed in Patent Document 2 may prevent damage to a transistor configured with low withstand voltage elements. Thus, similar to Patent Document 1, Patent Document 2 suggests a technical concept which considers a withstand voltage of the level shift circuit.
FIG. 11 shows the level shift circuit illustrated in FIG. 1 of Patent Document 2, in which reference numerals are changed and some reference numerals are added.
A level shift circuit 20 includes an input circuit 21, a shift circuit 22, and a voltage generation circuit 23. The level shift circuit 20 is supplied with two power supply voltages, namely, a low power supply voltage VD1 and a high power supply voltage VD2. The input circuit 21 is operated by the low power supply voltage VD1, and the shift circuit 22 and the voltage generation circuit 23 are operated by the high power supply voltage VD2. The level shift circuit 20 converts an input signal IN having a low power supply voltage VD1 into an output signal OUT having a high power supply voltage VD2.
The input circuit 21 is configured as an inverter circuit including a first p channel MOS transistor (hereinafter, referred to as a “pMOS transistor”) Q21 and a first n channel MOS transistor (hereinafter, referred to as an “nMOS transistor”) Q22.
A source S of the first pMOS transistor Q21 is connected to the low power supply voltage VD1, and a source S of the first nMOS transistor Q22 is connected to ground GND. In the input circuit 21, the input signal IN is supplied to a common gate G of the first pMOS transistor Q21 and the first nMOS transistor Q22, and an inverted input signal /IN obtained by inverting the input signal IN is output to a common drain D. In other words, in response to the input signal IN, the input circuit 21 outputs the input signal IN and the inverted input signal /IN to the shift circuit 22.
The shift circuit 22 includes first to sixth transistors Q23 to Q28. First and second transistors Q23 and Q24 are pMOS transistors, and third to sixth transistors Q25 to Q28 are nMOS transistors.
Sources of the first and second transistors Q23 and Q24 are connected to the high power supply voltage VD2, and gates G thereof are connected to drains D of the second and first transistors Q24 and Q23.
Sources S of the third and fourth transistors Q25 and Q26 are connected to ground GND. The inverted input signal /IN is supplied to a gate G of the third transistor Q25, and the input signal IN is supplied to a gate G of the fourth transistor Q26. Drains D of the third and fourth transistors Q25 and Q26 are connected to sources S of fifth and sixth transistors Q27 and Q28, respectively.
Respective drains D of the fifth and sixth transistors Q27 and Q28 are connected to respective drains D of the first and second transistors Q23 and Q24. Gates G of the fifth and sixth transistors Q27 and Q28 are commonly connected to the voltage generation circuit 23. An output signal OUT is output from a common connection point between the drain D of the first transistor Q23 and the drain D of the fifth transistor Q27.
The third and fourth transistors Q25 and Q26 are configured with low withstand voltage elements, each having a low element withstand voltage, such that they can be turned on or off in response to the input signal IN and the inverted input signal /IN supplied to the respective gates G. Meanwhile, the first and second transistors Q23 and Q24 and the fifth and sixth transistors Q27 and Q28 are configured with high withstand voltage elements whose element withstand voltage is set to correspond to the high power supply voltage VD2.
The voltage generation circuit 23 includes transistors Q29 to Q36. A prescribed bias voltage Vn11 is taken from a node N11 installed between the high power supply voltage VD2 and ground GND, and the bias voltage Vn11 is supplied to the common gate G of the fifth and sixth transistors Q27 and Q28. Meanwhile, the voltage generation circuit 23 generates the gate voltage of the fifth and sixth transistors Q27 and Q28, i.e., the bias voltage Vn11, such that the third and fourth transistors Q25 and Q26, which are low withstand voltage elements, do not break. The voltage generation circuit 23 turns on the transistor Q29 and turns off the transistor Q35 using a high level control signal CNTL. An inverter circuit comprised of the transistors Q29 and Q35 outputs a low level signal to a gate of the transistor Q30 to turn on the transistor Q30.
In FIG. 11, the high power supply voltage VD2 is set to be, for example, 3V and the low power supply voltage VD1 is set to be, for example, 1V. A withstand voltage between the sources and drains of the third and fourth transistors Q25 and Q26, which are low withstand voltage elements, is set to be 1.5V, and a withstand voltage between the source and drains of the first, second, fifth, and sixth transistors Q23, Q24, Q27, and Q28, which are high withstand voltage elements, is set to be 3.0V. The voltage between the gates and sources of the high withstand voltage elements is set to be 0.5V. Accordingly, the bias voltage Vn11 generated by the voltage generation circuit 23 and supplied to the gate G of the fifth and sixth nMOS transistors Q27 and Q28 is about half of the high power supply voltage VD2 and does not break the third and fourth transistors Q25 and Q26.
The third and fourth transistors Q25 and Q26 are configured with low withstand voltage elements which are driven by the low power supply voltage VD1 and have a low withstand voltage between a source and drain thereof. Based on the high power supply voltage VD2, the bias voltage Vn11 which does not break the third and fourth transistors Q25 and Q26 is generated by the voltage generation circuit 23 and supplied to the gates G of the fifth and sixth transistors Q27 and Q28. Accordingly, when the first and second transistors Q23 and Q24 are turned on, the high power supply voltage VD2, exceeding the withstand voltage between the source and drain, is prevented from being applied to the third and fourth transistors Q25 and Q26. Namely, by limiting the voltage applied from the high power supply voltage VD2, the third and fourth transistors Q25 and Q26 configured with low withstand voltage elements are prevented from being broken.
Japanese Patent Laid-Open Publication No. 2003-235251 (“Patent Document 3”), which was filed by the applicant of the present application, discloses a switching regulator. In particular, Patent Document 3 discloses the use of a bootstrap circuit as a voltage supply of a level shift circuit.
Patent Document 1 focuses on a withstand voltage of a MOS transistor constituting a level shift circuit. However, it does not suggest the use of the level shift circuit for a switching regulator. Patent Document 2 suggests a voltage generation circuit which prevents damage to transistors constituting a level shift circuit. However, since the voltage generation circuit is configured to respond to a control signal CNTL, the circuit configuration is complicated. Patent Document 3 discloses a level shift circuit and a switching regulator, but does not suggest operating the level shift circuit depending on the operation of the switching regulator.